Theory and Performance of Narrow Correlator Spacing in a GPS Receiver

TLDR

Conventional GPS receivers use 1.0‑chip early‑late correlator spacing, but narrowing the spacing offers advantages that outweigh the need for higher bandwidth and sampling rates, which modern CMOS technology can meet. The paper derives and validates the performance benefits of narrow correlator spacing in GPS receivers. Narrow spacing reduces noise by canceling correlated early‑late noise components and mitigates multipath by preserving a cleaner DLL discriminator. Simulations and tests confirm that narrow spacing lowers tracking errors under noise and multipath conditions.

Abstract

Historically, conventional GPS receivers have used 1.0 chip early-late correlator spacing in the implementation of delay lock loops (DLLs). However, there are distinct advantages to narrowing this spacing, especially in C/A-code tracking applications. These advantages are the reduction of tracking errors in the presence of both noise and multipath. The primary disadvantage is that a wider precorrelation bandwidth is required, coupled with higher sample rates and higher digital signal processing rates. However, with current CMOS technology, this is easily achievable and well worth the price. Noise reduction is achieved with narrower spacing because the noise components of the early and late signals are correlated and tend to cancel, provided that early and late processing are simultaneous (not dithered). Multipath effects are reduced because the DLL discriminator is less distorted by the delayed multipath signal. This paper presents the derivation of these narrow correlator spacing improvements, verified by simulated and tested performance.