"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC

TLDR

The design assumes that two identical ADCs sampling the same input should produce equal outputs, so a zero difference indicates correct calibration. A split‑ADC architecture divides the die into two independent converters that simultaneously sample the input; their outputs are averaged for the final code while the difference drives a background calibration loop that adjusts parameters, with a multiple‑residue amplifier ensuring distinct decision trajectories. Self‑calibration is achieved in roughly 10 k conversions, and the 16‑bit, 1‑MS/s ADC built in 0.25‑µm CMOS consumes 105 mW and occupies a 1.2 mm × 1.4 mm die.

Abstract

Self-calibration in approximately 10 000 conversions is demonstrated in a 16-bit, 1-MS/s algorithmic analog-to-digital converter (ADC). Continuous digital background calibration is enabled by introduction of a "split ADC" architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog sub-system of the ADC is implemented in 0.25-/spl mu/m CMOS, consumes 105 mW, and has a die size of 1.2 mm /spl times/ 1.4 mm.