Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

Abstract

An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-/spl mu/m nonsilicided, a 0.35-/spl mu/m silicided, and a 0.25-/spl mu/m silicided shallow-trench-isolation bulk CMOS processes.