A CMOS mismatch model and scaling effects

Abstract

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a /spl radic/n-law model is developed for modeling gate-finger dependence of mismatch.