Oxidation-sharpened gated field emitter array process

Abstract

Structural and electrical characteristics of silicon field emitter arrays are reported. The authors present a process using anisotropic etching of silicon, and silicon oxidation, to form self-aligned gated field emitter structures. The process uses plasma etching and oxidation to form the field emission tips, and allows control of the aspect ratio of the devices. Processing limits and process latitude are discussed. The authors observed average currents of 0.3 mu A/emitter in 1300-emitter arrays, and the emission is stable at 5*10/sup -8/ torr. The arrays exhibit a soft failure behavior, where individual emission tips fail as the gate voltage is increased, but the array as a whole continues to operate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>