30-nm Tunnel FET With Improved Performance and Reduced Ambipolar Current

Abstract

This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate.