IEEE Transactions on Electron Devices · 2011 · 137 citations · 22 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice CharacterizationField-effect TransistorsIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsSemiconductor HeterostructuresThin-film TransistorsDual-gate Field-effect TransistorsGate Oxide Thickness EffectsSiliconSilicon-on-insulator TechnologyTunneling Field-effect Transistors
This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate.
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Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors
Joerg Appenzeller, Yu-Ming Lin, Joachim Knoch et al. · Physical Review Letters · 2004 · 880 citations
Complementary tunneling transistor for low power application
Pengzhan Wang, K. Hilsenbeck, T. Nirschl et al. · Solid-State Electronics · 2004 · 519 citations
Engineering, Electrical Engineering, Electronic Materials +10