IEEE Transactions on Circuits and Systems I Regular Papers · 2012 · 19 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyGate Drive CircuitsIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsMixed-signal Integrated Circuit DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos Digital Circuit DesignCmos Logic CircuitsComplementary Metal-oxide-semiconductor BiasingHigh-speed Cmos DesignHigh-speed I/o Circuit DesignVoltage
This paper proposes a high speed bidirectional mixed-voltage I/O buffer using 90 nm 1.2 V standard CMOS process. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit/receive <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$2\times{\rm VDD}$</tex></formula> voltage level signal without any gate-oxide overstress hazard. Most important of all, the gate-oxide overstress hazard is eliminated by adopting a dual-path gate-tracking circuit. The maximum data rate and jitter are measured to be 800 Mbps/12.37 ps and 704 Mbps/14.79 ps for 1.2 V and 2.5 V signal voltage, respectively, with a given capacitive load of 20 pF.
13