Electronics Letters · 1994 · 13 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesClock Distribution NetworksClock ManagementCmos Circuit DesignJitter AnalysisMixed-signal Integrated Circuit DesignTiming AnalysisClock Data RecoveryClock JitterClock Jitter AnalysisClock Network CharacterizationClock RecoveryDielectric Resonator FiltersJitterTiming Jitter
The design and characterisation of a 20 Gbit/s clock recovery unit developed for the RACE 2011 project of the European Community is reported. This unit is based on an open loop structure using a dielectric resonator narrowband filter. The jitter results show that the approach provides a robust and low cost solution for the clock extraction problem at very high bit rates.
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