Clock Network Characterization

Clock Network Characterization is a method that analytically models the timing, skew, jitter, and power integrity attributes of a clock distribution network to enable precise evaluation and optimization of its performance within synchronous digital systems.

35

Publications

1.8K

Citations

139

Authors

55

Institutions

Publications per year

2017–2026

2

Authors

139

  1. CH
    Charlotte Helfrich‐Förster

    University of Würzburg, Germany

    3 publications · 191 citations

    3

    h-index

  2. TY
    Taishi Yoshii

    Okayama University, Japan

    2 publications · 146 citations

    2

    h-index

  3. KS
    K. Sundaresan

    Georgia Institute of Technology, United States

    2 publications · 251 citations

    2

    h-index

  4. KL
    Kenneth L. Shepard

    Columbia University, United States

    2 publications · 72 citations

    2

    h-index

  5. FA
    Farrokh Ayazi

    Georgia Institute of Technology, United States

    2 publications · 251 citations

    2

    h-index

1–5 of 139

Venues

  1. IEEE Journal of Solid-State Circuits

    6 publications · 574 citations

    6

    h-index

  2. The Journal of Comparative Neurology

    2 publications · 146 citations

    2

    h-index

  3. Electronics Letters

    1 publications · 13 citations

    1

    h-index

  4. IEEE Transactions on Nuclear Science

    1 publications · 21 citations

    1

    h-index

  5. IEEE Design & Test of Computers

    1 publications · 35 citations

    1

    h-index

1–5