Concepedia

Analysis and Implementation of Practical, Cost-Effective Networks on Chips

IEEE Design & Test of Computers · 2005 · 46 citations · 17 references

Concepts

EngineeringHigh Performance Computer NetworkEdge ComputingMesh NetworkComputer EngineeringNetwork AnalysisSystems EngineeringComputer ArchitectureCost-effective NetworksDesign IssuesInternet Of ThingsNetwork On ChipInterconnection Network ArchitectureHigh-speed NetworkingInterconnection NetworkMesochronous CommunicationBurst Packet Transactions

Abstract

This article describes design issues in three NoCs (network on chip) that exploit star and mesh networks, with the objective of comparing area and energy costs. We present new solutions based on mesochronous communication and burst packet transactions.

References

17

Route packets, net wires

William J. Dally, Brian Towles · 2001 · 3.2K citations

Engineering, Network Routing, On-chip Interconnection Networks +20

The design and implementation of a first-generation CELL processor

D. Pham, S. Asano, M. Bolliger et al. · 2005 · 546 citations

Engineering, Vlsi Design, Power Architecture Processor +18

DyAD

Jingcao Hu, Radu Mărculescu · 2004 · 495 citations

Network Routing Algorithm, Engineering, Edge Computing +8

Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip

Davide Bertozzi, Luca Benini · IEEE Circuits and Systems Magazine · 2004 · 415 citations

Engineering, Customized Noc, Computer Architecture +16

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

E. Rijpkema, Kees Goossens, A. Rădulescu et al. · Design, Automation, and Test in Europe · 2003 · 377 citations

Combined Router, Engineering, Computer Architecture +17