1969 · 15 citations · 2 references
Hardware ModelingEngineeringAccurate SimulationVerificationComputer ArchitectureSimulationFormal VerificationTiming AnalysisProgrammable Logic ArrayModeling And SimulationParallel ComputingDesign VerificationCcurate Timing InformationComputer EngineeringComputer ScienceLogic SynthesisPropagation Delay AmbiguityCircuit DesignFormal MethodsParallel ProgrammingFunctional Verification
This paper presents a design verification logic simulation system which uses a ccurate timing information and propagation delay ambiguity in its circuit models.
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Programming languages for non-numeric processing---2