Analog-to-digital converter error diagnosis

Abstract

Following published procedures for characterizing ADCs using phase-plane error functions, this paper shows how a given calibration data set may used to extract estimates of: specific error performance features pertaining to ADC architectural considerations. The procedure requires the selection of basic functions based upon properties of a desired feature. The techniques are applied to the 8-bit TKAD20 operating at 204.8 MSPS to illustrate the concepts discussed in the paper. Results show how it is possible to estimate hysteresis and average sample time errors versus the state of the ADC. A simple consideration shows why it is not possible to separate sample time errors from the effects of nonlinear capacitance and a first ever diagnosis yields sample-time jitter versus ADC state.