Electronics Letters · 2001 · 12 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingHigh-frequency Semiconductor DevicesIntegrated Circuit DesignMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsCmos Analog Integrated CircuitsCmos Radio-frequency CircuitsCmos ScalingMaximum SpeedPower ConsumptionScaling Effects In CmosSilicon-on-insulator CmosSilicon-on-insulator Technology
Dual-phase dynamic pseudo-NMOS ([DP]2) frequency dividers have been implemented in a partially scaled 0.1 µm CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]2 latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V.
2
High-speed CMOS circuit technique
Jiren Yuan, C. Svensson · IEEE Journal of Solid-State Circuits · 1989 · 792 citations
Engineering, Computer Engineering, Electrical Engineering +16
A 26.5 GHz silicon MOSFET 2:1 dynamic frequency divider
M. Wetzel, L. Shi, K.A. Jenkins et al. · IEEE Microwave and Guided Wave Letters · 2000 · 30 citations