Low power secure AES S-box using adiabatic logic circuit

Abstract

Numerous works on advanced encryption standard (AES) S-box architecture have been done using composite field arithmetic in Galois field. However, to the best of our knowledge, less information is available on both a secure circuit and the low power consumption. In this work, we implement our previous proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using multi-stage positive polarity Reed-Muller (PPRM) representation over composite field technique. The logic sharing method for frequently same logic function usage in the combination logic is applied. Consequently, the low-complexity, high resistive and the low-power consumption are achieved. The results in this paper are obtained from the SPICE simulation with 0.18-μm 1.8-V standard CMOS technology at operating frequency of 1.25-70 MHz. Base on the logic speed, security performance and low-power requirement, we deduce that our proposed logic is applicable for contactless smart cards, RFID tags, and wireless sensors.