A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor

Abstract

A modeling strategy for high voltage VDMOS transistors based on the intrinsic drain voltage and the use of EKV MOSFET model as a core for the intrinsic MOS channel is presented. The proposed charge based model correctly reproduces the special effects of high voltage devices like the quasi saturation, impact ionization and self heating. The accuracy of the model is better than 5% for DC I-V and g-V characteristics. We also report the accurate simulation of the intrinsic drain voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</sub> , which represents the basis of the AC model. The unique peaks on C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> characteristics peculiar to high voltage devices are accurately simulated by this charge based model. It is demonstrated that this model provides excellent trade-off between speed, convergence and accuracy, being suitable for circuit simulation in any operation regime of HV MOSFETs including all special effects of these devices