2011 · 16 citations · 9 references
Low-power ElectronicsMillimeter Wave TechnologyEngineeringCascode AmplifierRf SemiconductorMixed-signal Integrated CircuitAnalog DesignComputer EngineeringNoise2.9-Db Noise FigureLna StagesMicroelectronicsLowest Noise FigureRf SubsystemElectromagnetic Compatibility
This paper discusses a two-stage low noise amplifier (LNA) implemented in a 45nm CMOS SOI process that operates between 43 and 53 GHz. The LNA stages are based on a cascode amplifier with simultaneous noise and input power matching. The LNA exhibits a minimum noise figure (NF) of 2.9 dB at 47 GHz and measured gain of 18.5 dB at 49 GHz. The output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> compression power is 3 dBm and saturation output power is 7 dBm to reach a peak efficiency of 22%. The measured OIP3 is 14 dBm. The LNA occupies an area of 0.35mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with pads and consumes 19 mA from 1.2 V supply. The results present the lowest noise figure for a silicon-based millimeter-wave LNA.
9
C.H. Doan, Sohrab Emami, Ali M. Niknejad et al. · IEEE Journal of Solid-State Circuits · 2005 · 708 citations
Electrical Engineering, Millimeter-wave Cmos Design, Engineering +12
Millimeter-Wave Integrated Circuits in 65-nm CMOS
Mikko Varonen, Mikko Kärkkäinen, Mikko Kantanen et al. · IEEE Journal of Solid-State Circuits · 2008 · 120 citations
Electrical Engineering, 65-Nm Baseline Cmos, Engineering +11