Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis

Abstract

Source/drain (S/D) series resistance components and device/process parameters contributing to series resistance are extensively analyzed using advanced model for future CMOS design and technology scaling into the nanometer regime. The total series resistance of a device is found to be very sensitive to the variations of the sidewall thickness, the doping concentration in the deep junction region, and the Schottky barrier height of the silicide contact. A prediction of series resistance trends with technology generation indicates that silicide-diffusion contact resistance and overlap resistance will be major components in the total series resistance of nanometer-scale CMOS transistors scaled according to the ITRS roadmap. The key factors for challenging scaling barriers related to parasitic resistance are quantitatively examined as a function of technology scaling and it is shown that the series resistance can be substantially reduced through controlling both the abruptness of the S/D junction profile and the silicide Schottky barrier engineering.