A Layout Structure for Matching Many Integrated Resistors

Abstract

A proposed mirrored shuffle layout pattern cancels systematic resistor gradient variations up to second order and allows monolithic integration of hundreds of matched resistors for precision analog circuits. A test circuit uses 15 000 subresistors and three levels of interconnect to form 150 main resistors in a 2.85/spl times/0.83 mm/sup 2/ area. It demonstrates better than 11-b matching. The dominant remaining error is related to a layout artifact external to the core resistor array, and after separation the resistor array itself achieves over 13-b matching. Wafer maps show significant first- and second-order resistor value gradients that are cancelled to within the measurement error.