A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

Abstract

A fault injection tool for Virtex FPGAs based on the fault emulation technique is presented. It allows injection of faults in the configuration control mechanism differently from the tools developed so far, which address only configuration memory cells and user registers. This permits a more realistic and complete study of device behaviour, especially in those applications in which the system operating in a harsh environment undergoes frequent reconfigurations. Injection is performed by modifying the configuration bit stream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar. This makes our tool independent of the system used for design development and allows a quick fault injection. Moreover, any register of the configuration state machine can be accessed and the effect of SEUs on them analyzed. This analysis is fundamental before performing radiation ground testing of this kind of device.