A fault injection tool for SRAM-based FPGAs

Abstract

A fault injection tool for SRAM-based FPGAs based on the fault emulation technique is presented. Faults are injected by modifying the configuration bitstream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar. This makes our tool independent of the system used for design development and allows a quick fault injection. Also, any device configuration cell can be accessed and this permits to study the effects of possible contentions or shorts, which cannot be analyzed using commercial tools. An example of the use of the tool is described.