IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 1994 · 44 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsClock ManagementCmos Circuit DesignTiming AnalysisAdder DesignAddersArithmetic Logic Unit DesignCmos Logic CircuitsCmos Logic DesignCoding Scheme DesignMultiplier DesignMultiply-accumulate Units
This paper describes the design of a pipelined CMOS 16/spl times/16 redundant binary multiplication-and-accumulation (MAC) unit. The MAC unit uses a novel coding scheme for representing binary signed digits. The coding, integrated with the modified Booth algorithm, produces a factor of four reduction in the number of summands feeding the adder tree without preprocessing. The consequent chip layout is compact and small. Furthermore, the MAC's pipeline stages are balanced, resulting in a clock rate exceeding 200 MHz with 0.8-/spl mu/m two-level metal CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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