Twin-Tub CMOS II-An advanced VLSI technology

Abstract

An advanced CMOS technology has been developed for the fabrication of VLSI circuits having 2.5 µm features. The structure uses Twin-Tubs in a lightly-doped n-epitaxial layer over an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -substrate <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Local oxidation and self-aligned chan-stops provide device isolation. The gate level has a nominal sheet resistance of 2.5Ω/□ and consists of a composite layer of TaSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> over n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> polysilicon. The gate oxide is 350 Å thick, and the electrical channel lengths for the n- and p-channel transistors are nominally 1.5 µm The threshold voltages of the n- and p-channel devices are 0.7V and -1.1V respectively. A compensating threshold-adjustment implant is used to tailor the p-channel threshold voltage. The limitations and advantages of this technique are addressed here. We present the process highlights discuss the device properties and present some of the applications of this technology.