Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current

Abstract

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n/sup +/ and p/sup +/ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p/sup +/-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits.