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Thermal stress induced delamination of through silicon vias in 3-D interconnects
123
Citations
4
References
2010
Year
Unknown Venue
EngineeringMechanical EngineeringSilicon ViasSilicon On InsulatorInterconnect (Integrated Circuits)Damage MechanismSteady StateAdvanced Packaging (Semiconductors)Microstructure-strength Relationship3-D InterconnectsElectronic PackagingThermomechanical AnalysisMaterials Science3D Ic ArchitectureDurability PerformanceTsv DelaminationSolid MechanicsSemiconductor Device FabricationHeat TransferMicroelectronicsLow-cycle FatigueMicrostructureThermal StressApplied PhysicsInterfacial DelaminationThermal EngineeringMechanics Of Materials
In this paper we investigated the interfacial delamination of through silicon via (TSV) structures under thermal cycling or processing. First finite element analysis (FEA) was used to evaluate the thermal stresses and the driving force of TSV delamination. Then, the modeling results were validated by analytical solutions of the crack driving force deduced for a long crack at the steady state. Both results were found to be in good agreement at the steady state and together they suggested a fracture mechanism to account for the TSV delamination observed. The analytical solution further provided a basic framework for studying the impact of materials, process and structural design on reliability of the TSV structure. In particular, we found that reducing the TSV diameter yields a definite advantage in lowering the crack driving force. In addition, annular TSVs and an overlaying metal pad on a TSV can reduce the crack driving force for delamination during thermal cycling. Finally, the metallization effect was investigated for four TSV materials: copper, aluminum, nickel, and tungsten. Tungsten was found to have the smallest crack driving force due to the least thermal mismatch with the surrounding silicon. The reliability implication was discussed.
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