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Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction
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2008
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EngineeringThree-dimensional Stress EngineeringInf XmlnsSemiconductor DeviceNanoelectronicsElectronic EngineeringStressMobility/on-current EnhancementSide-surface PfinfetsElectronic PackagingCurrent ReductionDevice ModelingElectrical EngineeringPhysicsBias Temperature InstabilityMicroelectronicsStress-induced Leakage CurrentApplied PhysicsUniaxial Stress EffectsMechanics Of Materials
In this paper, the first systematic study of uniaxial stress effects on mobility (μ)/on-current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> ) enhancement and gate current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> ) reduction in FinFETs is described. We demonstrate for the first time that I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher μ/I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> enhancement ratio by longitudinal strain and comparable/higher short-channel I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dsat</inf> . Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.