2005 · 23 citations · 19 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksSystem-on-chip DesignInterprocess CommunicationMultiprocessor SystemsNetwork-on-chip DesignPerformance ModelingProcessor Core DesignTask Scheduling2D Mesh TopologyContention ModelingNetwork ContentionNetwork-on-chipNetwork-on-chip ArchitecturesTest CasesThroughputThroughput-aware Scheduling
Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this paper, we propose a switch which employs the latency insensitive concepts and applies the round-robin scheduling techniques to achieve high communication resource utilization. Based on the assumptions of the 2D-mesh network topology constructed by the switch, this work not only models the communication and the contention effect of the network, but develops a communication-driven task binding algorithm that employs the divide and conquer strategy to map applications onto the multiprocessor system-on-chip. The algorithm attempts to derive a binding of tasks such that the overall system throughput is maximized. To compare with the task binding without consideration of communication and contention effect, the experimental results demonstrate that the overall improvement of the system throughput is 20% for 844 test cases.
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A note on two problems in connexion with graphs
E. Dijkstra · Numerische Mathematik · 1959 · 23.8K citations
Networks on chips: a new SoC paradigm
Luca Benini, Giovanni De Micheli · Computer · 2002 · 3.7K citations · Full text
An Algorithm for Path Connections and Its Applications
C. Y. Lee · IEEE Transactions on Electronic Computers · 1961 · 1.6K citations
A network on chip architecture and design methodology
Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen et al. · 2003 · 1.2K citations