Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing

Abstract

This brief proposes a bias-and-input interchanging (BII) technique for resetting opamp summing nodes to remove the memory effect of residue signals in cyclic/pipelined analog-to-digital converters (ADCs) with opamp-sharing architectures. The proposed BII technique does not need an additional preamplifier stage or need to sacrifice signal swing, as do other opamp summing node resetting (OSNR) techniques. Thus, the size of driving circuits and power consumption can be reduced. In the BII technique, fully differential (FD) BII folded-cascode and pseudodifferential (PD) BII telescopic opamp architectures are developed. The proposed FD-BII technique is more power efficient than existing OSNR techniques. The proposed PD-BII technique can further save more power and opamp area than the FD-BII technique, but the problem of common-mode (CM) offset amplification accompanies the PD architecture. This brief proposes simple floating interconnection schemes that eliminate the CM offset amplification for the PD architecture. Compared with existing OSNR techniques, the proof-of-concept ADCs confirm that the proposed BII technique can be used by ADCs to reset opamp summing nodes more efficiently, using less power and achieving a wider signal swing.