Logic Optimization for Majority Gate-Based Nanoelectronic Circuits

Abstract

In this paper, an efficient majority logic optimizer is proposed to synthesize majority gate-based nanoelectronic circuits. A novel sharing and mapping scheme is proposed to achieve simple synthesized circuits and high synthesis speed. The experimental results show that compared to the existing method, the proposed method achieves up to 20% reduction of gate counts and 25% higher synthesis speed. This proposed optimizer can be widely used in quantum cellular automata, tunneling phase logic, and single electron tunneling circuit design