Low power IC clock tree design

Abstract

When reliability to process variations becomes an important issue, wires in the clock-tree must be made extremely wide to limit the process skew to a specified tolerable value. Due to the resultant increase in the overall capacitance, the power dissipation in clock-net is dramatically increased. We demonstrate that in spite of buffer mismatches and an additional component of power dissipation due to their short-circuit currents, the clock tree power can be significantly reduced by buffer insertion given the constraint on allowable process-variation dependent skew and maximum current densities (electromigration).