Investigation on ESD Transient Immunity of Integrated Circuits

Abstract

This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a very fast transmission line pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full- custom 0.18 mum CMOS IC.