Automatic sizing of power/ground (P/G) networks in VLSI

Abstract

This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while electromigration and voltage drops constraints are fulfilled. The algorithm proposed here runs 50% faster than the best methods reported for tree type network topologies.