Arbitration and routing impact on NoC design

Abstract

The increasing number of processing elements packed inside integrated circuits requires communication architectures such as a Networks-on-Chip (NoCs) to deal with scalability, bandwidth and energy consumption goals. Many different NoC architectures have been proposed, and several experiments reveal that routing and arbitration schemes are key design features for NoC performance. Therefore, this work proposes a routing scheme called planned source routing, which is implemented in a NoC architecture with distributed arbitration called Hermes-SR. The paper compares Hermes-SR to the Hermes NoC that employs distinct arbitration and routing mechanisms and algorithms. One set of experiments enables to confront design time planned source routing and runtime distributed routing. Additionally, the paper presents the advantages of using deadlock free adaptive routing algorithms as basis for balancing the overall communication load in both routing mechanisms. Another experiment reveals the tradeoffs between using centralized or distributed arbitration. A last evaluation exposes the performance advantages of combining distributed arbiters with planned source routing. Results enforce that design time planned source routing tends to avoid NoC congestion and contributes for average latency reduction, while distributed arbitration optimizes NoC saturation figures.