A high speed super self-aligned bipolar-CMOS technology

Abstract

An ideal device structure for integrating bipolar and CMOS is reported in this paper. Both the vertical npn and MOS devices have new non-overlapping super self-aligned structures. With a single 5V supply, averaged per stage delay of 82ps and 125ps have been measured for 0.6µm and 0.85µm (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> ) CMOS ring oscillators. Bipolar transistors have also been fabricated with a nominal current gain of 100.