Testability features of the 68040

Abstract

The design and implementation of on-chip test functions on the 68040 microprocessor are described. The discussion includes an introduction to the 68040, along with the testability goals and objectives that were set at the beginning of the design. Further discussions detail the different design-for-testability techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the 68040.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>