Improved Subthreshold Swing and Gate-Bias Stressing Stability of p-Type $\hbox{Cu}_{2}\hbox{O}$ Thin-Film Transistors Using a $\hbox{HfO}_{2}$ High-$k$ Gate Dielectric Grown on a $\hbox{SiO}_{2}/\hbox{Si}$ Substrate by Pulsed Laser Ablation

Abstract

p-Type Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O thin films and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectrics are deposited by pulsed laser ablation. p-Type Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O metal-oxide-semiconductor capacitors and thin-film transistors (TFTs) are then fabricated and investigated. Experimental results show that a HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -stacked gate dielectric can effectively improve interface properties and decrease gate-leakage current when compared with a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric. Thus, increased mobility, a decreased subthreshold swing, and enhanced gate-bias-voltage stressing stability have been achieved for the relevant Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O TFTs. Bottom-gate and top-source/drain-contact p-channel Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O TFTs ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 500/20 μm) with the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -stacked gate dielectric exhibit superior performance with a saturation-carrier-mobility value of 2.7 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s, an on-off current ratio of 1.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , a subthreshold swing of 137 mV/dec, and a threshold-voltage shift of 1.4 V after gate-bias stress at 10 V for 3600 s.