A fresh look at retiming via clock skew optimization

Abstract

The introduction of clock s k ew at an edge-triggered ipop has an eect that is similar to the movement of the ip-op across combinational logic module boundaries, and these are continuous and discrete optimizations with the same eect. While this fact has been recognized before, this work, for the rst time, utilizes this information to nd a minimum/specied period retiming eciently. The clock period is guaranteed to be at most one gate delay larger than a tight l o w er bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.