Lifetime Prediction of SnPb and SnAgCu Solder Joints of Chips on Copper Substrate Based on Crack Propagation FE-Analysis

Abstract

It is necessary to improve the lifetime prediction based on FE-methods of different electronic packages in order to reduce the time and costs of new developments. This paper purposes a method describing the crack propagation of chip on copper substrate solder joints. The chips that were studied are power transistors. They were soldered on copper substrate (NiAu metallization) with two different solder alloys (SnPb eutectic and SAC 305). The chip dimensions and the solder joint thickness have an influence on the lifetime, so that two different chips with two different solder thicknesses were used as test specimens. These were thermally loaded, and the state of the solder joints was regularly checked. Three different kind of methods were used to characterize the damage of solder joints: the scanning acoustic microscope (SAM) detects the crack initiation and propagation; the cross section analysis can validate the results of the scanning acoustic microscope and can show the microstructure changes; and the thermal resistance which is influenced by the damage of the solder joint was measured and correlated to damage. After presenting the results of these investigations, a general FE-method predicting the crack initiation and propagation using the Paris laws is presented