Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply

Abstract

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2- mu m technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5- mu m technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2- mu m gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>