Barrier-first integration for improved reliability in copper dual damascene interconnects

Abstract

A new PVD barrier process is demonstrated that eliminates critical dimension (CD) loss and copper contamination of intra-layer dielectric (ILD) caused by conventional argon sputter precleans. In this process, a layer of Ta(N) is first deposited to protect the via sidewalls from contamination, then an RF bias is applied to the wafer during subsequent barrier deposition such that there is a net etch (resputter) from the bottom of the vias. The resputter step allows effective removal of Cu oxide and etch-residues without contamination of the dielectric with resputtered copper, and without faceting of the ILD. This barrier-first scheme improves via resistance, ILD reliability, via stress migration and electromigration performance relative to a conventional argon sputter preclean.