VLSI design synthesis with testability

Abstract

A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom up and top down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example was used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST with different test schedules were explored. Design Scores comprised of area, delay, fault coverage, and test length were computed and graphed. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.