Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

Abstract

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work.