A process for the combined fabrication of ion sensors and CMOS circuits

Abstract

A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2- mu m, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si/sub 3/N/sub 4/ acts both as the pH-sensitive insulator for the ISFETs and as a protection layer for the on-chip circuitry buried beneath it. A source-follower circuit is described that provides an output voltage dependent on the threshold-voltage variations of the sensing transistor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>