A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection

Abstract

The practical goal of this study is to develop an efficient design solution for the control of the holding voltage of thyristor-type structures (ones operating in the left part of S-shape I-V characteristic), thereby making them suitable for use in mixed-signal and in power supply protection circuits. This specific design is applied to the cascoded LVTSCR structures and validated on the basis of ESD test structures and I/O cells. The research objective was to control the avalanche-injection conductivity modulation by the emitter injection of the device level, thereby achieving control of the section of the S-shape I-V curve responsible for the holding voltage.