Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Abstract

Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup +/ and p/sup +/ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less.