At-speed on-chip diagnosis of board-level interconnect faults

Abstract

This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults.This approach is based on a new parallel test pattern generator and a specifically fault detecting sequence. The test sequence has tree major advantages.At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chp at-speed fault diagnosis of interconnect faults.Third, the hardware implementation of both the test generator and the response analyzer is very efficient in terms of silicon area.