A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

Abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhbox m$</tex> CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hbox mm^2$</tex> and has a peak-to-peak jitter of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$pm $</tex> 6.6 ps at 1.3 GHz.