IEEE Journal of Solid-State Circuits · 1988 · 20 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignParallel ComputingCmos Circuit DesignMemory Hierarchy DesignMemory Subsystem DesignMicroarchitecture DesignParallel ArchitecturesParallel Computer ArchitectureAssociative ProcessingContent-addressable MemoryContent-addressable Memory (Cam)Control RequirementsDesign MethodologyMemory Circuit DesignParallel ProcessingStatic Cmos Logic
The authors discuss the design, development and implementation of the 9-kb (256-word*37-bit) associative memory used in the single-chip array processing element (SCAPE) chip, a CMOS VLSI associative parallel processor (APP) that integrates 256 associative processing elements (APEs) on a single 68-pad chip to achieve high-speed, cost-effective image and signal processing. It is shown that a static CMOS content-addressable memory (CAM) design is unsuited to the constraints of the SCAPE chip architecture and that a purely nMOS CAM cell provides the best compromise between the conflicting area, speed, power, and control requirements. Comprehensive details of this design are given together with an evaluation of its performance. Finally, a description of the design methodology used in the construction of the SCAPE chip is presented with a breakdown of circuit areas and operational data.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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