The Associative Linear Array Processor

Abstract

The associative linear array processor (ALAP) is a new approach to making large associative processors practical. Data storage in shift registers, bit-serial arithmetic, LSI word cells comprehensive arithmetic capability within the memory array, and electronic fault isolation are all utilized. The processor is a linear array of word cells, each containing memory and arithmetic logic. All connections to the word cells are by means of common buses except for the multiuse chaining channel. As with most operations within word cells, the current function of the chaining channel in each word is controlled by the combination of common control lines and the states of flag flip-flops in each word. This allows different chaining channel action in different words. Among its many uses the chaining channel can be used to resolve conflicts of multiple associative memory matches, to perform interword arithmetic, or to sort data as they are being input to the associative memory. In the ALAP project effort conducted at Hughes, wafers containing arrays of ALAP cells have been fabricated using LSI technology. A complete hardware/software system using the ALAP has been fabricated and checked out, along with two application programs of nontrivial magnitude.