A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation

Abstract

An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for modern microprocessor systems. Clock recovery and I/O circuitry perform to specification across multiple DRAM manufacturers' processes. The clock-recovery circuitry is described in depth for areas that are sensitive to power-supply noise. I/O circuitry for preserving signal integrity in high-speed bussed systems is described. Design methodology that enables rapid simulation and verification of the design in each fabrication process is discussed. Logic that enables interleaved transactions with concurrent operation is detailed. Computer-aided-design tools for large aspect merged logic/memory are discussed. Last, measured results are summarized showing clock jitter, setup and hold timing, and period versus V/sub dd/ operation.