Inter-die signaling in three dimensional integrated circuits

Abstract

This work discusses a three dimensional network on chip (3D NoC) fabricated in the 0.18 mum MIT Lincoln Laboratories 3D FDSOI 1.5 V process. As a proof of concept, a three tier, 27 node, NoC test chip occupying 4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per tier was designed and tested. It is the first of its kind to demonstrate successful inter-tier signaling in a complex three dimensional design, and validates the technology as a viable alternative to the continued scaling of conventional CMOS processes. Simulated results show that when implemented in this 3D process, simple 3D mesh interconnection networks allow for the sharing of global routing resources for complex systems while consuming an extremely low 2 mW of power per transaction. Using these results, we establish the need for a 3D network simulator to quantify the advantage 3D circuit implementations have over 2D.